1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of source/drain regions of transistors by using an embedded strain-inducing semiconductor material to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
In integrated circuits, a great number of circuit elements are formed in and above an appropriate semiconductor layer, which, for the vast majority of semiconductor devices, is currently comprised of silicon, due to the virtually unlimited availability and the long-term experience gained over the last decades with respect to the processing of silicon and related materials. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with a lightly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, in view of increased integration density and performance enhancement of individual field effect transistors, the continuous reduction of the channel length has become a dominant criterion for designing integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. Among others, the development or sophisticated adaptation of enhanced photolithography techniques, implantation processes, deposition techniques, etch processes and many other processes may be necessary with the advance to every new technology node. Moreover, reducing the channel length of the transistors may also require a reduction of the thickness of the gate insulation layer in order to maintain sufficient controllability of the channel region during operation of the device. For sophisticated transistor architectures, the thickness of gate insulation layers based on silicon dioxide materials have reached 2 nm or less, thereby rendering a further scaling of silicon dioxide based gate dielectrics a less than desirable strategy for future device generations due to the significant increase of gate leakage currents.
Therefore, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the silicon-based channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to an advanced technology node while avoiding or at least postponing many of the above process developments and adaptations associated with device scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure of the silicon in the channel region by, for instance, producing a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of silicon-based transistor devices formed in a silicon layer of standard crystallographic characteristics increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials and manufacturing techniques.
In one frequently employed approach, the hole mobility of PMOS transistors is enhanced by forming an embedded strained mixed silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. During the incorporation of the silicon/germanium alloy into the drain and source regions of the PMOS transistors, these regions are selectively recessed to form a cavity with a specified depth, while the NMOS transistors are masked. Subsequently, the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth. Although this technique offers significant advantages in view of performance gain of the PMOS transistor and thus of the entire CMOS device, the corresponding process flow for forming the recesses and for refilling the recesses by the desired semiconductor alloy may comprise a plurality of complex process steps, as will now described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, comprising a P-channel transistor 150p and an N-channel transistor 150n, which may be formed above a substrate 101 at appropriate substrate areas. In this manufacturing stage, the transistors 150p, 150n my each comprise a gate electrode 105, formed above a semiconductor layer 102 and separated therefrom by a gate insulation layer 104. Moreover, the respective gate electrodes may be covered by a capping layer 109, which is typically comprised of silicon nitride. As previously explained, the transistors 150p, 150n may represent field effect transistors of highly scaled semiconductor devices, wherein a gate length, i.e., the horizontal extension of the gate electrodes 105 in FIG. 1a, may be approximately 100 nm and significantly less. Consequently, in order to obtain an enhanced performance for the P-channel transistor 150p for a given gate length, strain may be created in the respective channel region 103 based on an embedded strained semiconductor layer to be formed adjacent to the gate electrode 105 of the P-channel transistor 150p, as will be described later on.
Typically, the semiconductor device 100 as shown in FIG. 1a may be formed according to the following processes. After forming a dielectric material for the gate insulation layers 104 by oxidation and/or deposition, and after the deposition of an appropriate gate electrode material, such as polysilicon, an advanced patterning process on the basis of photolithography and anisotropic etch techniques may be performed to obtain the gate electrodes 105 as shown. In order to provide a reliable encapsulation of the gate electrodes 105 during the further processing, an appropriate capping layer is usually deposited prior to the patterning of the gate electrodes 105, wherein a thickness of the corresponding capping layer may be selected such that an appropriate process margin is provided for the subsequent processing, that is, during the subsequent etch and epitaxial growth processes. Consequently, the capping layers 109 are provided on top of the gate electrodes 105 with a thickness corresponding to the process requirements, wherein, however, the thickness of the capping layers 109 may also be selected in accordance with requirements of the preceding patterning process, thereby also restricting the available range of thickness for the capping layers 109.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. A spacer layer stack comprising a silicon dioxide liner 107 and a silicon nitride spacer layer 106 is conformally formed above the first and second transistors 150p, 150n. Moreover, a resist mask 108 is formed above the N-channel transistor 150n, while exposing the P-channel transistor 150p. 
The liner 107 and the spacer layer 106 may be formed on the basis of well-established techniques, such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) and the like. During the formation of the liner 107, which will act as an etch stop layer during an anisotropic etch process 110 for patterning the spacer layer 106, an appropriate thickness of the layer 107 is selected with respect to a reliable protection of the capping layers 109 and the semiconductor layer 102 during a respective extended over-etch time of the process 110, which may be required due to pattern-dependent etch non-uniformities, which may also be referred to as microloading effects. Consequently, the initial thickness of the silicon dioxide liner 107 is selected in a range of approximately 10-20 nm in order to provide the required protection of the underlying materials during the anisotropic etch process 110.
Thereafter, the spacer layer 106, comprised of silicon nitride, may be deposited on the basis of LPCVD and the like, with a thickness required for reliably encapsulating the second transistor 150n during a subsequent selective epitaxial growth process and also to define a specific offset for a cavity etch in the P-channel transistor 150p. Thereafter, the resist layer 108 may be formed on the basis of well-established photolithography techniques. Then, the device 100 is subjected to the anisotropic etch process 110 in order to form respective sidewall spacers on the gate electrode 105 of the P-channel transistor 150p to provide the required encapsulation for the subsequent selective epitaxial growth process. During the etch process 110, appropriate process parameters for a highly anisotropic behavior of the etch process 110 may be obtained, for instance, on the basis of fluorine-containing reactive components in combination with a specific plasma ambient, while a high etch selectivity with respect to the material of the liner 107 is simultaneously achieved. The pronounced selectivity of the etch process 110 may, however, be associated with a certain degree of non-uniformity and sensitivity to pattern density of circuit elements formed across the entire substrate 101, thereby resulting in a moderately non-uniform etch result. Consequently, a certain amount of over-etch time in the process 110 is applied in order to reliably expose the liner 107 across the entire substrate 101. At the same time, exposure of the semiconductor layer 102 and/or the capping layers 109 is to be maintained at a low level in order to not unduly affect the uniformity of the subsequent cavity etch process. Thus, a more or less reduced uniformity of the oxide liner 107 after the completion of the etch process 110 may therefore also affect the finally obtained etch result in the subsequent cavity etch process. Additionally, the characteristics of the respective spacers formed during the anisotropic etch process 110, i.e., their finally obtained width, as well as the degree of coverage of the sidewalls of the gate electrode 105, may also be affected by the required over-etch time and thus the thickness of the spacer layer 106 and also of the capping layers 109 may not be selected independently from each other, but may have to be selected on the basis of the requirement for an efficient protection during the subsequent processing.
FIG. 1c schematically illustrates the semiconductor device 100 after the completion of the above-described process sequence and after a further plasma-based resist strip etch process for removing the resist mask 108. Hence, the device 100 comprises respective spacer elements 106A, including the liner 107 formed on sidewalls of the gate electrode of the P-channel transistor 150p, while the N-channel transistor 150n is still covered by the liner 107 and the spacer layer 106. As explained above, a respective spacer width 106W, as well as a residual thickness 107T of the liner 107 after the etch process 110, may depend on the specifics of the etch process and may vary due to the above-explained etch non-uniformities. Thereafter, the device 100 is subjected to a further etch process for removing the exposed portions of the residues of the liner 107, which may have a significantly reduced thickness, i.e., the thickness 107T, compared to the initial thickness, which may be accomplished on the basis of high frequency plasma-based techniques. Thereafter, the device 100 may be subjected to a cleaning process on the basis of an appropriate wet chemical chemistry for efficiently removing any contaminants resulting from the previous process steps. Any contaminants or surface irregularities, caused by the preceding etch processes, may otherwise significantly influence the subsequent cavity etch process, thereby resulting in non-uniformities, which may then also translate into respective non-uniformities during a subsequent selective epitaxial growth process.
FIG. 1d schematically illustrates the device 100 after the completion of the above-described process sequence, wherein, here, the device 100 is exposed to a further etch process 112 for forming a respective recess or cavity 111 adjacent to the gate electrode 105 on the basis of the sidewall spacers 106A. The etch process 112 may be designed as an isotropic etch process, an anisotropic etch process or as any mixture thereof, depending on the desired size and shape of the recess 111. Due to any process non-uniformities, especially during the etch process 110 for patterning the sidewall spacers 106A, the etch process 112 may also result in corresponding etch non-uniformities, i.e., the depth of the cavity 111 as well as the resulting surface roughness may vary across the substrate 101. Since the etch process 112 and thus the finally obtained depth and shape of the recess 111 may be controlled for a given etch recipe on the basis of the etch time only, any previously produced non-uniformities may significantly determine the finally obtained across-substrate uniformity in addition to any further process non-uniformities of the cavity etch process 112 itself.
After the etch process 112 and any cleaning processes for removing contaminants from exposed portions of the semiconductor layer 101, a corresponding selective epitaxial growth process may be performed in order to provide a strained semiconductor material in the recess 111, for instance, a silicon/germanium layer, thereby providing a desired degree of strain in the adjacent channel region 103. The selective epitaxial growth process is itself a highly complex process, the result of which may depend on a plurality of interrelated process parameters, such as flow rates, pressure, temperature, dopant species and the like. Consequently, in addition to any non-uniformities of the respective recesses 111, the strain generated by the epitaxially grown material and other characteristics thereof may be affected by a plurality of process parameters of the overall process flow. As a consequence, corresponding non-uniformity of transistor characteristics may result. For these reasons, sophisticated metrology procedures have been developed which strive to detect process fluctuations, for instance with respect to the complex cavity etch process and/or the selective epitaxial growth process. To this end, conventionally optical inspection techniques involving sophisticated and time-consuming evaluation procedures are employed. Due to the high complexity of these monitoring techniques, the amount of measurement data gathered is limited, since otherwise a significant loss of throughput would result.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.